The workshop will focus on key areas of the INPACE Cluster dedicated to “Enabling technologies - Chips for the future” and is aligned with the topics defined in the Digital Partnerships between EU and Japan. The presentations and discussions will cover the many semiconductor challenges (complex value chain, computing and storage needs, novel functionalities for electronic systems, circuit and system integration, energy & material needs, reliability) and possible technological solutions, especially: reductions of energy and material consumption for sustainable electronic systems, advanced logic devices and materials, integration of novel functionalities for future electronic systems (e.g. smart sensing, energy harvesting for autonomous system, power devices, photonics, cryoelectronics for quantum engineering), heterogeneous 3D integration and packaging for high performance, low power, low latency, miniaturisation, integration of new functionalities and lower cost of electronic systems, and possible cooperation on gaps in the semiconductor value chain.
This workshop is associated with the newly launched "Japan and EU Semiconductors: Mutual Innovation & Excellence" JASMINE Project.
Organiser: Dr. Francis Balestra, SiNANO Institute/CNRS, France, INPACE Co-organiser: Prof. Ken Uchida, The University of Tokyo, Japan
Day 2: Wednesday, 25 March 08:45-10:00 Session 1 - Heterogeneous Integration and Advanced Packaging 10:15-11:25 Session 2 - New Channel Materials 11:25-12:15 Session 3 - Semiconductor Technology, value chain and projects for possible international cooperation 13:30-14:20 Session 4 - Power Devices 14:20-15:10 Session 5 - Memory Technologies 15:25-16:15 Session 6 - Optoelectronics 16:15-16:40 Session 7 - Semiconductor Technology, value chain and projects for possible International Cooperation 16:40-17:05 Plenary 17:05-17:30 Closing Remarks